As gigascale silicon technology approaches the 50 nm generation and beyond, the performance of a monolithic system-on-a-chip (SoC) has failed by progressively greater margins to reach the “intrinsic limits” of each particular generation of technology. The root cause of this failure is the fact that the capabilities of monolithic silicon technology per se have vastly surpassed those of the ancillary or supporting technologies that are essential to the full exploitation of a high performance SoC. The most serious obstacle that blocks fulfillment of the ultimate performance of a SoC is inferior heat removal. The increase in clock frequency of a SoC has been virtually brought to a halt by the lack of acceptable ways for removing, for example, 200 W from a 15×15 mm die. A huge deficit in chip input/output (I/O) bandwidth due to tack of I/O interconnect density is the second most serious deficiency stalling high performance gains. The excessive access time of a chip multiprocessor (CMP) for communication with its off-chip main memory is a direct consequence of the lack of, for example, a low latency 100 THz bandwidth I/O signal network. Lastly, SoC performance has been severely constrained by inadequate I/O interconnect technology capable of supplying, for example, 200–400 A at 0.5 V to a CMP.
Accordingly, there is a need in the industry to address the aforementioned deficiencies and/or inadequacies.